1. Field of the Invention
The present invention generally relates to an ATA (advanced technology attachment) interfaced Circuit and a signal encoding method and, more particularly, to a Circuit and a corresponding method for reducing the number of serial ATA external PHY (physical layer) signals. The Circuit employs a configuration in which digital means and analog means are separated so as to install the high-frequency analog circuit portion into an external PHY chip. The behavior of the PHY signals and the characteristic of 10-bit data encoding are also utilized to encode the control signals as well as the status signals into the multi-level interface signals or into a special 10-bit data encoding on the data bus so as to significantly reduce the number of required PHY signals.
2. Description of the Prior Art
In recent years, with the high development in information-related industries, people have increasing needs for a higher operation speed as well as a higher data transmission rate in the computer system. In view of this, the industries have made lots of efforts to improve the data transmission rate on the data storage system. For example, the earliest ATA interface proving a data transmission rate of 16 MBps (mega bytes per second) has been replaced by the follow-ups such as the ATA33 interface proving a data transmission rate of 33 MBps, the ATA66 interface proving a data transmission rate of 66 MBps and the modern-day ATA100, ATA133, etc. With a parallel data transmission scheme, however, the fore-mentioned ATA interface specifications have suffered from a need for more signal lines as well as an interfering noise, leading to severer limit for signal line length as well as improvement in data transmission rate.
More recently, a novel serial ATA interface has been presented to the public, in which the data transmission rate increases to 1.5 Gbps (giga bit per second) for the first generation serial ATA interface and is expected to be 3.0 Gbps for the second generation serial ATA interface and even 6.0 Gbps for the third generation serial ATA interface. Moreover, there are only four signal lines required for data transmission and the allowed signal line length can be prolonged.
However, as the serial ATA interfaced products are still under intensive development, parallel ATA interfaced products dominate the market. In order to look after both sides, the manufacturers of computer products would rather choose to support both the parallel ATA interface and the serial ATA interface.
To operate in coordination with the upgraded transmission rate of the data storage system as well as the compatibility between the product specifications, some manufacturers have proposed various solutions. Please refer to, for example, FIG. 1, which is a block diagram schematically illustrating the configuration of a conventional ATA interface configuration. In FIG. 1, a storage medium controller 121 in a host controller chip 12 (for example, a south bridge chip) comprises a serial ATA PHY 123, through which the storage medium controller 121 is connected to a serial ATA device 16 (for example, a serial ATA hard disk). The storage medium controller 121 is also connected to a parallel ATA device 18 (for example, a parallel ATA hard disk) through an IDE bus 14. In this configuration, both the parallel ATA interfaced device and the serial ATA interfaced device can be supported; however, the serial ATA PHY 123 typically occupies a larger area due to its high-frequency analog applications. Therefore, host controller chip 12 containing the serial ATA PHY 123 has to have a large area high speed analog function with it, which leads to poor fabrication yield as well as high fabrication cost.
In view of this, there is need in providing a new solution to the problems related to the conventional circuit configuration. A simple but effective Circuit is disclosed in the present invention to minimize the number of interface signals, lower the fabrication cost and improve the yield.